Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Those patterned material layers on the semiconductor wafer are aligned and configured to form one or more functional circuits. Photolithography systems are used to pattern a semiconductor wafer. When semiconductor technology continues progressing to circuit layouts having smaller feature sizes, a lithography system with higher resolution is need to image an IC pattern with smaller feature sizes. An electron-beam (e-beam) system is introduced for lithography patterning processes as the electron beam has wavelengths that can be tuned to very short, resulting in very high resolution. An e-beam lithography can write small features to a wafer but takes longer time. The corresponding fabrication cost is higher and cycle time is too long. A reflective e-beam lithography system having a digital pattern generator is used to generate an e-beam pattern with the reduced cycle time. However, multiple pixels of the digital pattern generator encounter misalignment on wafer pixels due to clock skew.
It is desired, therefore, to provide an e-beam lithography system and a method for e-beam lithography patterning in IC fabrication to address the above issues.